Network switches are widely used among a plurality of nodes to share open sources. For example, a network switch can be used to connect a plurality of computers or other devices such as network printers or network storages. Referring to FIG. 1, a conventional network switch 1 principally comprises a control chip 10, a clock source 11, and a plurality of input/output (I/O) ports. The control chip 10 is formed with a switch matrix 100 for controlling data flows among a plurality of media access controllers (MACs) B1˜Bn, an embedded memory 102 and a phase-locked loop (PLL) clock signal generator 103. For each input/output (I/O) port, a physical device (PHY) A1˜An is in communication with one of the media access controller B1˜Bn. In response to a reference clock signal generated from the clock source 11, the PLL clock signal generator 103 generates a clock signal, which is referred by various units to coordinate operations in the control chip 10. Via the physical layers A1˜An, the media access controllers B1˜Bn communicate with the corresponding network nodes to conduct data transmission.
In practice, bandwidths of network interface cards used in the network nodes connected to the same network switch are likely to differ from one another. Currently, network interface cards of three kinds of bandwidth specifications, i.e. 10, 100 and 1000 Mb/s, are commonly used with the physical devices A1˜An. Alternatively, it is possible for any of the physical devices A1˜An to remain floating. Even if some of the I/O ports of the network switch 1 do not connect to any network node, the frequency of the clock signal provided by the PLL clock signal generator 103 in the prior art still has to conform to the maximal bandwidth requirement just in case that all the I/O ports may be occupied with the highest bandwidth.
For example, for a network switch having two I/O ports supporting three kinds of bandwidth specifications (10/100/1000 Mb/s) and the other twenty two I/O ports supporting two kinds of bandwidth specifications (10/100 Mb/s), the PLL clock signal generator 103 should be designed to generate a high frequency clock signal adapted to the situation that all the I/O ports are operated under their highest bandwidths. The required frequency of the clock signal is generally up to 100 M/s. For supplying such a high frequency clock signal, the control chip 10 always operates at a high speed so as to result in the high temperature and high power consumption of the network switch, or possibly, halt the network switch.